Design space exploration of Ferroelectric FET based Processing-in-Memory DNN Accelerator

2019/08/12 by Yoon, Insik, Jerry, Matthew, Datta, Suman +1
#Emerging Technologies (cs.ET) #FOS: Computer and information sciences #FOS: Electrical engineering #Neural and Evolutionary Computing (cs.NE) #Signal Processing (eess.SP) #electronic engineering #information engineering

paper · doi:10.48550/arxiv.1908.07942

Abstract

In this letter, we quantify the impact of device limitations on the classification accuracy of an artificial neural network, where the synaptic weights are implemented in a Ferroelectric FET (FeFET) based in-memory processing architecture. We explore a design-space consisting of the resolution of the analog-to-digital converter, number of bits per FeFET cell, and the neural network depth. We show how the system architecture, training models and overparametrization can address some of the device limitations.

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