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The Post-Silicon Semiconductor Era: A Review of Physics, Synthesis, and Architectural Integration of Carbon Nanotube Field-Effect Transistors

2025/08/31 by Suhas Suresh Bharadwaj, Bharadwaj, Suhas Suresh, Reuben Thomas Thovelil +10 · 1 citation
Engineering · Materials Science · #Carbon Nanotubes in Composites #Chemical and Physical Properties of Materials #Nanotechnology research and applications #cond-mat.mes-hall #physics.app-ph

paper · pdf · doi:10.48550/arxiv.2509.00947

openalex publication_date 2025/08/31 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Silicon CMOS scaling is approaching a set of hard physical limits. Direct source-to-drain quantum tunneling, an unscalable subthreshold swing, and the thermal ceiling known as Dark Silicon motivate the search for a new channel material that can carry logic scaling forward. This review builds the case for single-walled carbon nanotubes (SWCNTs) as that material. We follow a continuous narrative from electronic-structure theory through synthesis to integration. The SWCNT bandgap and its near-ballistic transport limits are derived from the graphene zone-folding framework and the Landauer-Buttiker formalism. We benchmark these theoretical limits against ideal coaxial electrostatic bounds to evaluate how well the geometry suppresses short-channel effects before quantum tunneling takes over. Comparing this analytical framework against published 5 nm experimental data illustrates the aggressive subthreshold degradation driven by source-to-drain tunneling. Furthermore, we derive the exact areal-density equivalence between 1D and 2D quantum capacitance. This demonstrates that even close-packed arrays cannot fully close the dimensional gap to 2D materials, underscoring why superior carrier velocity and electrostatics must carry the CNTFET advantage. Next, we examine CoMoCAT growth and aqueous two-phase extraction against the semiconducting-purity demands of logic fabrication, alongside contact engineering and reversible chemical doping. A closing techno-economic analysis weighs this physics and process picture against IEEE IRDS roadmap projections and environmental health constraints. Taken together, the evidence points to materials purification, contact reliability, and bias temperature instability as the remaining practical barriers to commercial CNTFET adoption.

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