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Hardware-Efficient Randomized Compiling

2024/06/20 by Neelay Fruitwala, Akel Hashim, Fruitwala, Neelay +17 · 1 citation
Computer Science · #Algorithms and Data Compression #Computability, Logic, AI Algorithms #Distributed and Parallel Computing Systems #FOS: Physical sciences #Quantum Physics (quant-ph)

paper · pdf · doi:10.48550/arxiv.2406.13967

openalex publication_date 2024/06/20 · openalex created_date 2025/10/10 · openalex updated_date 2026/08/01

Abstract

Randomized compiling (RC) is an efficient method for tailoring arbitrary Markovian errors into stochastic Pauli channels. However, the standard procedure for implementing the protocol in software comes with a large experimental overhead -- namely, it scales linearly in the number of desired randomizations, each of which must be generated and measured independently. In this work, we introduce a hardware-efficient algorithm for performing RC on a cycle-by-cycle basis on the lowest level of our FPGA-based control hardware during the execution of a circuit. Importantly, this algorithm performs a different randomization per shot with zero runtime overhead beyond measuring a circuit without RC. We implement our algorithm using the QubiC control hardware, where we demonstrate significant reduction in the overall runtime of circuits implemented with RC, as well as a significantly lower variance in measured observables.

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