SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST

2025/07/04 by Caviglia, Alessio, Marostica, Filippo, Carpegna, Alessio +2
#Computer Vision and Pattern Recognition (cs.CV) #FOS: Computer and information sciences #Neural and Evolutionary Computing (cs.NE)

paper · doi:10.48550/arxiv.2507.10561

Abstract

Hardware accelerators are essential for achieving low-latency, energy-efficient inference in edge applications like image recognition. Spiking Neural Networks (SNNs) are particularly promising due to their event-driven and temporally sparse nature, making them well-suited for low-power Field Programmable Gate Array (FPGA)-based deployment. This paper explores using the open-source Spiker+ framework to generate optimized SNNs accelerators for handwritten digit recognition on the MNIST dataset. Spiker+ enables high-level specification of network topologies, neuron models, and quantization, automatically generating deployable HDL. We evaluate multiple configurations and analyze trade-offs relevant to edge computing constraints.

Citations

• Training Spiking Neural Networks Using Lessons From Deep Learning
• Optuna: A Next-generation Hyperparameter Optimization Framework
• Surrogate Gradient Learning in Spiking Neural Networks
• Surrogate Gradient Learning in Spiking Neural Networks: Bringing the Power of Gradient-Based Optimization to Spiking Neural Networks
• The MNIST Database of Handwritten Digit Images for Machine Learning Research [Best of the Web]

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