2020/08/06 by Shilpa Mayannavar, Mayannavar, Shilpa, Uday Wali +1
Computer Science · Engineering · #Advanced Memory and Neural Computing #Embedded Systems Design Techniques #FOS: Computer and information sciences #Ferroelectric and Negative Capacitance Devices #Hardware Architecture (cs.AR) #Neural Networks and Applications #Parallel Computing and Optimization Techniques
paper · pdf · doi:10.48550/arxiv.2008.02584
openalex publication_date 2020/08/06 · openalex created_date 2022/07/26 · openalex updated_date 2026/07/28
The paper presents a systematic study and implementation of a reconfigurable\ncombinatorial multi-operand adder for use in Deep Learning systems. The size of\ncarry changes with the number of operands and hence a reliable algorithm to\nestimate exact number of carry bits is needed for optimal implementation of a\nreconfigurable multi-operand adder. A combinatorial multi-operand adder can be\nfaster compared to a sequential implementation using a two operand adder. Use\ncases for such adders occur in modern processors for deep neural networks. Such\nprocessors require massively parallel computing resources on chip. This paper\npresents a method to estimate the upper bound on the size of carry. A method to\ncompute the exact number of carry bits required for a multi-operand addition\noperation. A fast combinatorial parallel 4-operand adder module is presented.\nAn algorithm to reconfigure these adder modules to implement larger adders is\nalso described. Further, the paper presents two compact but slower iterative\nstructures that implement multi-operand addition, iterating with one column at\na time till the entire word is covered. Such serial/iterative operations are\nslow but occupy small space while parallel operations are fast but use large\nsilicon area on chip. Interestingly, the area-to-throughput ratio of two\narchitectures can tilt in favor of slower, smaller and large number units\ninstead of the fewer numbers of fast and large compute units. A lemma presented\nin the paper may be used to identify the condition when such tilt occurs.\nPotentially, this can save silicon space and increase the throughput of chips\nfor high performance computing. Simulation results of a 16 operand adder and\nusing an set of 4-operand adders for use in neural networks have been\npresented. Simulation results show that performance gain improves as the number\nof operations or operands increases.\n