2020/04/14 by F. Glaser, Giuseppe Tagliavini, Glaser, Florian +9
Computer Science · #Parallel Computing and Optimization Techniques #Interconnection Networks and Systems #Advanced Data Storage Technologies
paper · pdf · doi:10.48550/arxiv.2004.06662
The steeply growing performance demands for highly power- and\nenergy-constrained processing systems such as end-nodes of the\ninternet-of-things (IoT) have led to parallel near-threshold computing (NTC),\njoining the energy-efficiency benefits of low-voltage operation with the\nperformance typical of parallel systems. Shared-L1-memory multiprocessor\nclusters are a promising architecture, delivering performance in the order of\nGOPS and over 100 GOPS/W of energy-efficiency. However, this level of\ncomputational efficiency can only be reached by maximizing the effective\nutilization of the processing elements (PEs) available in the clusters. Along\nwith this effort, the optimization of PE-to-PE synchronization and\ncommunication is a critical factor for performance. In this work, we describe a\nlight-weight hardware-accelerated synchronization and communication unit (SCU)\nfor tightly-coupled clusters of processors. We detail the architecture, which\nenables fine-grain per-PE power management, and its integration into an\neight-core cluster of RISC-V processors. To validate the effectiveness of the\nproposed solution, we implemented the eight-core cluster in advanced 22nm FDX\ntechnology and evaluated performance and energy-efficiency with tunable\nmicrobenchmarks and a set of real-life applications and kernels. The proposed\nsolution allows synchronization-free regions as small as 42 cycles, over 41\ntimes smaller than the baseline implementation based on fast test-and-set\naccess to L1 memory when constraining the microbenchmarks to 10%\nsynchronization overhead. When evaluated on the real-life DSP-applications, the\nproposed SCU improves performance by up to 92% and 23% on average and energy\nefficiency by up to 98% and 39% on average.\n