2025/01/31 by Ran Ginosar, Ginosar, Ran
Computer Science · Engineering · #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Low-power high-performance VLSI design #VLSI and FPGA Design Techniques
paper · pdf · doi:10.48550/arxiv.2502.00153
openalex publication_date 2025/01/31 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
When a single core is scaled up to m cores occupying the same chip area and executing the same (parallelizable) task, achievable speedup is square-root m, power is reduced by square-root m and energy is reduced by m. Thus, many-core architectures can efficiently outperform architectures of a single core and a small-count multi-core.