2017/02/24 by Sándor P. Fekete, Fekete, Sándor P., Jan-Marc Reinhardt +3
Computer Science · Engineering · #Data Structures and Algorithms (cs.DS) #Embedded Systems Design Techniques #F.2.2 #FOS: Computer and information sciences #Interconnection Networks and Systems #VLSI and FPGA Design Techniques #cs.DS
paper · pdf · doi:10.48550/arxiv.1702.07696
11 pages, 12 figures; full version of extended abstract that appeared in ARCS 2016
arxiv created 2017/02/24 · openalex publication_date 2017/02/24 · arxiv updated 2017/02/27 · openalex created_date 2025/10/10 · openalex updated_date 2026/08/01
In the presence of dynamic insertions and deletions into a partially reconfigurable FPGA, fragmentation is unavoidable. This poses the challenge of developing efficient approaches to dynamic defragmentation and reallocation. One key aspect is to develop efficient algorithms and data structures that exploit the two-dimensional geometry of a chip, instead of just one. We propose a new method for this task, based on the fractal structure of a quadtree, which allows dynamic segmentation of the chip area, along with dynamically adjusting the necessary communication infrastructure. We describe a number of algorithmic aspects, and present different solutions. We also provide a number of basic simulations that indicate that the theoretical worst-case bound may be pessimistic.