Accelerator-aware Neural Network Design using AutoML

2020/03/05 by Suyog Gupta, Berkin Akin, Gupta, Suyog +1 · 2 citations
Computer Science · Engineering · #Advanced Memory and Neural Computing #Advanced Neural Network Applications #CCD and CMOS Imaging Sensors #FOS: Computer and information sciences #FOS: Electrical engineering #Machine Learning (cs.LG) #Machine Learning (stat.ML) #Signal Processing (eess.SP) #electronic engineering #information engineering

paper · pdf · doi:10.48550/arxiv.2003.02838

openalex publication_date 2020/03/05 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

While neural network hardware accelerators provide a substantial amount of raw compute throughput, the models deployed on them must be co-designed for the underlying hardware architecture to obtain the optimal system performance. We present a class of computer vision models designed using hardware-aware neural architecture search and customized to run on the Edge TPU, Google's neural network hardware accelerator for low-power, edge devices. For the Edge TPU in Coral devices, these models enable real-time image classification performance while achieving accuracy typically seen only with larger, compute-heavy models running in data centers. On Pixel 4's Edge TPU, these models improve the accuracy-latency tradeoff over existing SoTA mobile models.

Citations

• MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications
• ProxylessNAS: Direct Neural Architecture Search on Target Task and Hardware

Cited by

• Weight-Sharing Neural Architecture Search: A Battle to Shrink the Optimization Gap
• Apollo: Transferable Architecture Exploration

Related

• Rethinking Co-design of Neural Architectures and Hardware Accelerators
• Optimizing Neural Network for Computer Vision task in Edge Device
• Searching for Efficient Neural Architectures for On-Device ML on Edge TPUs
• Google Neural Network Models for Edge Devices: Analyzing and Mitigating\n Machine Learning Inference Bottlenecks
• AutoML for Multilayer Perceptron and FPGA Co-design