2021/10/14 by Sarbartha Banerjee, Banerjee, Sarbartha, Shijia Wei +5
Computer Science · Engineering · #Advanced Data Storage Technologies #Advancements in Semiconductor Devices and Circuit Design #Cryptography and Security (cs.CR) #FOS: Computer and information sciences #Parallel Computing and Optimization Techniques
paper · pdf · doi:10.48550/arxiv.2110.07157
openalex publication_date 2021/10/14 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Accelerators used for machine learning (ML) inference provide great performance benefits over CPUs. Securing confidential model in inference against off-chip side-channel attacks is critical in harnessing the performance advantage in practice. Data and memory address encryption has been recently proposed to defend against off-chip attacks. In this paper, we demonstrate that bandwidth utilization on the interface between accelerators and the weight storage can serve a side-channel for leaking confidential ML model architecture. This side channel is independent of the type of interface, leaks even in the presence of data and memory address encryption and can be monitored through performance counters or through bus contention from an on-chip unprivileged process.