2025/08/18 by Vo, Huynh Q. N., Chowdhury, Md Tawsif Rahman, Ramanan, Paritosh +2 · 1 citation
#Distributed #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #FOS: Electrical engineering #Hardware Architecture (cs.AR) #Parallel #Performance (cs.PF) #Systems and Control (eess.SY) #and Cluster Computing (cs.DC) #electronic engineering #information engineering
paper · doi:10.48550/arxiv.2508.13298
Exponential growth in global computing demand is exacerbated due to the higher-energy requirements of conventional architectures, primarily due to energy-intensive data movement. In-memory computing with Resistive Random Access Memory (RRAM) addresses this by co-integrating memory and processing, but faces significant hurdles related to device-level non-idealities and poor scalability for large computing tasks. Here, we introduce MELISO+ (In-Memory Linear Solver), a full-stack, distributed framework for energy-efficient in-memory computing. MELISO+ proposes a novel two-tier error correction mechanism to mitigate device non-idealities and develops a distributed RRAM computing framework to enable matrix computations exceeding dimensions of 65,000×65,000. This approach reduces first- and second-order arithmetic errors due to device non-idealities by over 90%, enhances energy efficiency by three to five orders of magnitude, and decreases latency 100-fold. Hence, MELISO+ allows lower-precision RRAM devices to outperform high-precision device alternatives in accuracy, energy and latency metrics. By unifying algorithm-hardware co-design with scalable architecture, MELISO+ significantly advances sustainable, high-dimensional computing suitable for applications like large language models and generative AI.