2023/12/28 by Yuanyuan Duan, Xingchen Liu, Duan, Yuanyuan +9 · 2 citations
Engineering · #3D IC and TSV technologies #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Low-power high-performance VLSI design #Machine Learning (cs.LG) #VLSI and FPGA Design Techniques
paper · pdf · doi:10.48550/arxiv.2312.16895
openalex publication_date 2023/12/28 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Chiplet-based systems have gained significant attention in recent years due to their low cost and competitive performance. As the complexity and compactness of a chiplet-based system increase, careful consideration must be given to microbump assignments, interconnect delays, and thermal limitations during the floorplanning stage. This paper introduces RLPlanner, an efficient early-stage floorplanning tool for chiplet-based systems with a novel fast thermal evaluation method. RLPlanner employs advanced reinforcement learning to jointly minimize total wirelength and temperature. To alleviate the time-consuming thermal calculations, RLPlanner incorporates the developed fast thermal evaluation method to expedite the iterations and optimizations. Comprehensive experiments demonstrate that our proposed fast thermal evaluation method achieves a mean absolute error (MAE) of 0.25 K and delivers over 120x speed-up compared to the open-source thermal solver HotSpot. When integrated with our fast thermal evaluation method, RLPlanner achieves an average improvement of 20.28% in minimizing the target objective (a combination of wirelength and temperature), within a similar running time, compared to the classic simulated annealing method with HotSpot.