2020/05/10 by Behzad Salami, Salami, Behzad, Osman Ünsal +3
Engineering · #Advanced Memory and Neural Computing #FOS: Computer and information sciences #FOS: Electrical engineering #Ferroelectric and Negative Capacitance Devices #Hardware Architecture (cs.AR) #Low-power high-performance VLSI design #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2005.04737
openalex publication_date 2020/05/10 · openalex created_date 2022/07/26 · openalex updated_date 2026/07/28
In this paper, we exploit the aggressive supply voltage underscaling\ntechnique in Block RAMs (BRAMs) of Field Programmable Gate Arrays (FPGAs) to\nimprove the energy efficiency of Multi-Layer Perceptrons (MLPs). Additionally,\nwe evaluate and improve the resilience of this accelerator. Through experiments\non several representative FPGA fabrics, we observe that until a minimum safe\nvoltage level, i.e., Vmin the MLP accuracy is not affected. This safe region\ninvolves a large voltage guardband. Also, it involves a narrower voltage region\nwhere faults start to appear in memories due to the increased circuit delay,\nbut these faults are masked by MLP, and thus, its accuracy is not affected.\nHowever, further undervolting causes significant accuracy loss as a result of\nthe fast-increasing high fault rates. Based on the characterization of these\nundervolting faults, we propose fault mitigation techniques that can\neffectively improve the resilience behavior of such accelerator. Our evaluation\nis based on four FPGA platforms. On average, we achieve >90% energy saving with\na negligible accuracy loss of up to 0.1%.\n