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Design and Evaluation of LAr Trigger Digitizer Board in the ATLAS Phase-I Upgrade

2018/06/21 by Kai Chen, H. Chen, Chen, Kai +21
Engineering · Physics and Astronomy · #FOS: Physical sciences #High Energy Physics - Experiment (hep-ex) #Instrumentation and Detectors (physics.ins-det) #Particle Accelerators and Free-Electron Lasers #Particle Detector Development and Performance #Particle physics theoretical and experimental studies

paper · pdf · doi:10.48550/arxiv.1806.08046

openalex publication_date 2018/06/21 · openalex created_date 2018/06/29 · openalex updated_date 2026/07/28

Abstract

The LHC upgrade is planned to enhance the instantaneous luminosity during Run 3 from 2021 through 2023. The Phase-I upgrade of the trigger readout electronics for the ATLAS Liquid Argon (LAr) Calorimeters will be installed during the second long shutdown of LHC in 2019-2020. In this upgrade, the so-called super cells are introduced to provide higher granularity, higher resolution and longitudinal shower shape information from the LAr calorimeters to the level-1 trigger processors. A new LAr Trigger Digitizer Board (LTDB) will manipulate and digitize 320 channels of super cell signals, and transmit it via 40 fiber optical links to the back end where data are further processed and transmitted to the trigger processors. Five pairs of bidirectional GBT links are used for slow control from the Front-end LInks eXchange (FELIX) in the ATLAS TDAQ system. LTDB also outputs 64 summed analog signals to the current Tower Builder Board via the new baseplane. A test system is developed to test all functions of the LTDB and carry out the performance measurement. A back end PCIe card is designed which has the circuit to interface to the ATLAS trigger, time and control system. It can control the generation of injection signals to the LTDB for performance test. It also configures and calibrate all ASICs on the LTDB.

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