2025/01/29 by Kevin López, Lopez, Kevin, Amin Rezaei +1
Engineering · #Advancements in PLL and VCO Technologies #Cryptography and Security (cs.CR) #FOS: Computer and information sciences #Low-power high-performance VLSI design #Radiation Effects in Electronics
paper · pdf · doi:10.48550/arxiv.2501.17402
openalex publication_date 2025/01/29 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
The outsourcing of semiconductor manufacturing raises security risks, such as piracy and overproduction of hardware intellectual property. To overcome this challenge, logic locking has emerged to lock a given circuit using additional key bits. While single-key logic locking approaches have demonstrated serious vulnerability to a wide range of attacks, multi-key solutions, if carefully designed, can provide a reliable defense against not only oracle-guided logic attacks, but also removal and dataflow attacks. In this paper, using time base keys, we propose, implement and evaluate a family of secure multi-key logic locking algorithms called Cute-Lock that can be applied both in RTL-level behavioral and netlist-level structural representations of sequential circuits. Our extensive experimental results under a diverse range of attacks confirm that, compared to vulnerable state-of-the-art methods, employing the Cute-Lock family drives attacking attempts to a dead end without additional overhead.