2020/10/01 by Nick Brown, Brown, Nick
Computer Science · #Distributed #Distributed and Parallel Computing Systems #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Parallel #Parallel Computing and Optimization Techniques #and Cluster Computing (cs.DC)
paper · pdf · doi:10.48550/arxiv.2010.00289
openalex publication_date 2020/10/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
The use of reconfigurable computing, and FPGAs in particular, has strong\npotential in the field of High Performance Computing (HPC). However the\ntraditionally high barrier to entry when it comes to programming this\ntechnology has, until now, precluded widespread adoption. To popularise\nreconfigurable computing with communities such as HPC, Xilinx have recently\nreleased the first version of Vitis, a platform aimed at making the programming\nof FPGAs much more a question of software development rather than hardware\ndesign. However a key question is how well this technology fulfils the aim, and\nwhether the tooling is mature enough such that software developers using FPGAs\nto accelerate their codes is now a more realistic proposition, or whether it\nsimply increases the convenience for existing experts. To examine this question\nwe use the Himeno benchmark as a vehicle for exploring the Vitis platform for\nbuilding, executing and optimising HPC codes, describing the different steps\nand potential pitfalls of the technology. The outcome of this exploration is a\ndemonstration that, whilst Vitis is an excellent step forwards and\nsignificantly lowers the barrier to entry in developing codes for FPGAs, it is\nnot a silver bullet and an underlying understanding of dataflow style\nalgorithmic design and appreciation of the architecture is still key to\nobtaining good performance on reconfigurable architectures.\n