2020/04/01 by Arman Kazemi, Kazemi, Arman, Ramin Rajaei +9
Computer Science · Engineering · #Advanced Memory and Neural Computing #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #Ferroelectric and Negative Capacitance Devices #Semiconductor materials and devices #cs.ET
paper · pdf · doi:10.48550/arxiv.2004.00703
Accepted at ISCAS'20 for oral presentation
arxiv created 2020/04/01 · openalex publication_date 2020/04/01 · arxiv updated 2020/04/03 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
An analog synapse circuit based on ferroelectric-metal field-effect transistors is proposed, that offers 6-bit weight precision. The circuit is comprised of volatile least significant bits (LSBs) used solely during training, and non-volatile most significant bits (MSBs) used for both training and inference. The design works at a 1.8V logic-compatible voltage, provides 1010 endurance cycles, and requires only 250ps update pulses. A variant of LeNet trained with the proposed synapse achieves 98.2% accuracy on MNIST, which is only 0.4% lower than an ideal implementation of the same network with the same bit precision. Furthermore, the proposed synapse offers improvements of up to 26% in area, 44.8% in leakage power, 16.7% in LSB update pulse duration, and two orders of magnitude in endurance cycles, when compared to state-of-the-art hybrid synaptic circuits. Our proposed synapse can be extended to an 8-bit design, enabling a VGG-like network to achieve 88.8% accuracy on CIFAR-10 (only 0.8% lower than an ideal implementation of the same network).