2021/12/20 by Vincent Tableau Roche, Roche, Vincent Tableau, Purushotham Murugappa Velayuthan +1
Computer Science · #Advanced Data Storage Technologies #Cloud Computing and Resource Management #Compiler #Computer science #Data flow diagram #Data-flow analysis #Dijkstra's algorithm #Distributed computing #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Loop tiling #Merge (version control) #Operating system #Parallel Computing and Optimization Techniques #Parallel computing #Scheduling (production processes) #Shortest path problem #Theoretical computer science #cs.AR
paper · pdf · doi:10.48550/arxiv.2112.10486
published in arXiv (Cornell University) (Cornell University) · The paper contains 7 pages and 10 figures. It is the result of the work performed during an internship at Nokia Bell Labs (Antwerp) in 2020
arxiv created 2021/12/20 · openalex publication_date 2021/12/20 · arxiv updated 2021/12/21 · openalex created_date 2022/05/05 · openalex updated_date 2026/07/28
Most of the previous works on data flow optimizations for Machine Learning hardware accelerators try to find algorithmic re-factorization such as loop-reordering and loop-tiling. However, the analysis and information they provide are still at very high level and one must further map them onto instructions that hardware can understand. This paper presents "Dijkstra-Through-Time" (DTT), an ahead of time compute and memory scheduling-mapping algorithm for deterministic workloads. It provides a simple implementation and supports accelerators with complex NoC configurations, at the expense of a long compilation process. This initial paper illustrates a proof of concept implementation to merge scheduling and data cache coherence mechanisms to get more optimized data flows.