2022/12/19 by Cemil Cem Gürsoy, Daniël Kraak, Gursoy, Cemil Cem +9
Computer Science · Engineering · #Advanced Data Storage Technologies #FOS: Computer and information sciences #Ferroelectric and Negative Capacitance Devices #Hardware Architecture (cs.AR) #Semiconductor materials and devices
paper · pdf · doi:10.48550/arxiv.2212.09356
openalex publication_date 2022/12/19 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Memory designs require timing margins to compensate for aging and fabrication process variations. With technology downscaling, aging mechanisms became more apparent, and larger margins are considered necessary. This, in return, means a larger area requirement and lower performance for the memory. Bias Temperature Instability (BTI) is one of the main contributors to aging, which slows down transistors and ultimately causes permanent faults. In this paper, first, we propose a low-cost aging mitigation scheme, which can be applied to existing hardware to mitigate aging on memory address decoder logic. We mitigate the BTI effect on critical transistors by applying a rejuvenation workload to the memory. Such an auxiliary workload is executed periodically to rejuvenate transistors that are located on critical paths of the address decoder. Second, we analyze workloads' efficiency to optimize the mitigation scheme. Experimental results performed with realistic benchmarks demonstrate several-times lifetime extension with a negligible execution overhead.