2010/11/11 by Giuseppe Carlo Tettamanzi, G. C. Tettamanzi, Tettamanzi, Giuseppe Carlo +16
Engineering · Physics and Astronomy · #Advancements in Semiconductor Devices and Circuit Design #FOS: Physical sciences #Integrated Circuits and Semiconductor Failure Analysis #Materials Science (cond-mat.mtrl-sci) #Mesoscale and Nanoscale Physics (cond-mat.mes-hall) #Semiconductor materials and devices #cond-mat.mes-hall #cond-mat.mtrl-sci
paper · pdf · doi:10.48550/arxiv.1011.2582
9 pages, 4 figures, *G.C.T. and A.P. contributed equally to this work
arxiv created 2010/11/11 · openalex publication_date 2010/11/11 · arxiv updated 2010/11/12 · openalex created_date 2022/10/06 · openalex updated_date 2026/07/28
The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.