2016/12/14 by Qian Ge, Yuval Yarom, Ge, Qian +5 · 2 voices
Computer Science · #Distributed systems and fault tolerance #Parallel Computing and Optimization Techniques #Security and Verification in Computing #cs.CR
paper · pdf · doi:10.48550/arxiv.1612.04474
openalex publication_date 2016/12/14 · openalex created_date 2017/08/31 · openalex updated_date 2026/07/28
Timing channels are information flows, encoded in the relative timing of events, that bypass the system's protection mechanisms. Any microarchitectural state that depends on execution history and affects the rate of progress of later executions potentially establishes a timing channel, unless explicit steps are taken to close it. Such state includes CPU caches, TLBs, branch predictors and prefetchers; removing the channels requires that the OS can partition such state or flush it on a switch of security domains. We measure the capacities of channels based on these microarchitectural features on several generations of processors across the two mainstream ISAs, x86 and ARM, and investigate the effectiveness of the flushing mechanisms provided by the respective ISA.We find that in all processors we studied, at least one significant channel remains. This implies that closing all timing channels seems impossible on contemporary mainstream processors.