2017/07/23 by Eshan Singh, Clark Barrett, Singh, Eshan +3
Computer Science · Engineering · #Advancements in Semiconductor Devices and Circuit Design #FOS: Computer and information sciences #Integrated Circuits and Semiconductor Failure Analysis #Logic in Computer Science (cs.LO) #Radiation Effects in Electronics #VLSI and Analog Circuit Testing
paper · pdf · doi:10.48550/arxiv.1707.07671
openalex publication_date 2017/07/23 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
During post-silicon validation, manufactured integrated circuits are\nextensively tested in actual system environments to detect design bugs. Bug\nlocalization involves identification of a bug trace (a sequence of inputs that\nactivates and detects the bug) and a hardware design block where the bug is\nlocated. Existing bug localization practices during post-silicon validation are\nmostly manual and ad hoc, and, hence, extremely expensive and time consuming.\nThis is particularly true for subtle electrical bugs caused by unexpected\ninteractions between a design and its electrical state. We present E-QED, a new\napproach that automatically localizes electrical bugs during post-silicon\nvalidation. Our results on the OpenSPARC T2, an open-source\n500-million-transistor multicore chip design, demonstrate the effectiveness and\npracticality of E-QED: starting with a failed post-silicon test, in a few hours\n(9 hours on average) we can automatically narrow the location of the bug to\n(the fan-in logic cone of) a handful of candidate flip-flops (18 flip-flops on\naverage for a design with ~ 1 Million flip-flops) and also obtain the\ncorresponding bug trace. The area impact of E-QED is ~2.5%. In contrast,\ndeter-mining this same information might take weeks (or even months) of mostly\nmanual work using traditional approaches.\n