2021/02/26 by Rakesh Kumar, Kumar, Rakesh, A. Martínez +4
Computer Science · #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Parallel Computing and Optimization Techniques
paper · pdf · doi:10.48550/arxiv.2102.13410
openalex publication_date 2021/02/26 · openalex created_date 2022/07/25 · openalex updated_date 2026/07/28
Hardware/Software (HW/SW) co-designed processors provide a promising solution\nto the power and complexity problems of the modern microprocessors by keeping\ntheir hardware simple. Moreover, they employ several runtime optimizations to\nimprove the performance. One of the most potent optimizations, vectorization,\nhas been utilized by modern microprocessors, to exploit the data level\nparallelism through SIMD accelerators. Due to their hardware simplicity, these\naccelerators have evolved in terms of width from 64-bit vectors in Intel MMX to\n512-bit wide vector units in Intel Xeon Phi and AVX-512. Although SIMD\naccelerators are simple in terms of hardware design, code generation for them\nhas always been a challenge. Moreover, increasing vector lengths with each new\ngeneration add to this complexity.\n This paper explores the scalability of SIMD accelerators from the code\ngeneration point of view. We discover that the SIMD accelerators remain\nunderutilized at higher vector lengths mainly due to: a) reduced dynamic\ninstruction stream coverage for vectorization and b) increase in permutations.\nBoth of these factors can be attributed to the rigidness of the SIMD\narchitecture. We propose a novel SIMD architecture that possesses the\nflexibility needed to support higher vector lengths. Furthermore, we propose\nVariable Length Vectorization and Selective Writing in a HW/SW co-designed\nenvironment to transparently target the flexibility of the proposed\narchitecture. We evaluate our proposals using a set of SPECFP2006 and\nPhysicsbench applications. Our experimental results show an average dynamic\ninstruction reduction of 31% and 40% and an average speed up of 13% and 10% for\nSPECFP2006 and Physicsbench respectively, for 512-bit vector length, over the\nscalar baseline code.\n