2012/05/10 by Rourab Paul, Sangeet Saha, Paul, Rourab +5
Computer Science · #Chaos-based Image/Signal Encryption #Coding theory and cryptography #Cryptographic Implementations and Security #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR)
paper · pdf · doi:10.48550/arxiv.1205.2153
openalex publication_date 2012/05/10 · openalex created_date 2022/10/01 · openalex updated_date 2026/07/28
Security is the most important part in data communication system, where more\nrandomization in secret keys increases the security as well as complexity of\nthe cryptography algorithms. As a result in recent dates these algorithms are\ncompensating with enormous memory spaces and large execution time on hardware\nplatform. Field programmable gate arrays (FPGAs), provide one of the major\nalternative in hardware platform scenario due to its reconfiguration nature,\nlow price and marketing speed. In FPGA based embedded system we can use\nembedded processor to execute particular algorithm with the inclusion of a real\ntime operating System (RTOS), where threads may reduce resource utilization and\ntime consumption. A process in the runtime is separated in different smaller\ntasks which are executed by the scheduler to meet the real time dead line using\nRTOS. In this paper we demonstrate the design and implementation of a 128-bit\nAdvanced Encryption Standard (AES) both symmetric key encryption and decryption\nalgorithm by developing suitable hardware and software design on Xilinx\nSpartan- 3E (XC3S500E-FG320) device using an Xilkernel RTOS, the implementation\nhas been tested successfully The system is optimized in terms of execution\nspeed and hardware utilization.\n