On Automating Proofs of Multiplier Adder Trees using the RTL Books

2025/07/25 by Manjrekar, Mayank
#FOS: Computer and information sciences #Logic in Computer Science (cs.LO) #Symbolic Computation (cs.SC)

paper · doi:10.48550/arxiv.2507.19010

Abstract

We present an experimental, verified clause processor ctv-cp that fits into the framework used at Arm for formal verification of arithmetic hardware designs. This largely automates the ACL2 proof development effort for integer multiplier modules that exist in designs ranging from floating-point division to matrix multiplication.

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