2021/04/29 by Jackson Melchert, Kathleen Feng, Melchert, Jackson +13
Computer Science · Engineering · #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #VLSI and Analog Circuit Testing #VLSI and FPGA Design Techniques #cs.AR
paper · pdf · doi:10.48550/arxiv.2104.14155
arxiv created 2021/04/29 · openalex publication_date 2021/04/29 · arxiv updated 2021/04/30 · openalex created_date 2021/05/10 · openalex updated_date 2026/07/28
The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy efficiency of an application running on the CGRA. This paper presents an automated approach for generating specialized PE architectures for an application or an application domain. Frequent subgraphs mined from a set of applications are merged to form a PE architecture specialized to that application domain. For the image processing and machine learning domains, we generate specialized PEs that are up to 10.5x more energy efficient and consume 9.1x less area than a baseline PE.