2019/04/12 by Milan Yadav, Yadav, Milan, Kanak Khanna +1
Computer Science · Energy · Engineering · #Currency Recognition and Detection #Energy Efficiency and Management #FOS: Computer and information sciences #FOS: Electrical engineering #Green IT and Sustainability #Performance (cs.PF) #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.1904.07813
openalex publication_date 2019/04/12 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Constraints imposed by power consumption and the related costs are one of the key roadblocks to the design and development of next generation exascale systems. To mitigate these issues, strategies that reduce the power consumption of the processor are the need of the hour. Techniques such as Dynamic Voltage and Frequency Scaling (DVFS) exist which reduce the power consumption of a processor at runtime but they should be used in such a manner so that their overhead does not hamper application performance. In this paper, we propose an energy saving strategy which operates on timeslice basis to apply DVFS under a user defined performance constraint. Results show energy savings up to 7% when NAS benchmarks are tested on a laptop platform