2023/04/06 by Nisarg Ujjainkar, Jingwen Leng, Ujjainkar, Nisarg +3 · 1 citation
Computer Science · Engineering · #Advanced Memory and Neural Computing #CCD and CMOS Imaging Sensors #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Parallel Computing and Optimization Techniques
paper · pdf · doi:10.48550/arxiv.2304.03352
openalex publication_date 2023/04/06 · openalex created_date 2023/04/11 · openalex updated_date 2026/07/28
Image processing algorithms are prime targets for hardware acceleration as they are commonly used in resource- and power-limited applications. Today's image processing accelerator designs make rigid assumptions about the algorithm structures and/or on-chip memory resources. As a result, they either have narrow applicability or result in inefficient designs. This paper presents a compiler framework that automatically generates memory- and power-efficient image processing accelerators. We allow programmers to describe generic image processing algorithms (in a domain specific language) and specify on-chip memory structures available. Our framework then formulates a constrained optimization problem that minimizes on-chip memory usage while maintaining theoretical maximum throughput. The key challenge we address is to analytically express the throughput bottleneck, on-chip memory contention, to enable a lightweight compilation. FPGA prototyping and ASIC synthesis show that, compared to existing approaches, accelerators generated by our framework reduce the on-chip memory usage and/or power consumption by double digits.