2024/04/08 by Paul Scheffler, Scheffler, Paul, Luca Colagrande +3 · 1 citation
Computer Science · #Advanced Data Storage Technologies #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Mathematical Software (cs.MS) #Parallel Computing and Optimization Techniques
paper · pdf · doi:10.48550/arxiv.2404.05303
openalex publication_date 2024/04/08 · openalex created_date 2024/04/11 · openalex updated_date 2026/07/28
Stencil codes are performance-critical in many compute-intensive applications, but suffer from significant address calculation and irregular memory access overheads. This work presents SARIS, a general and highly flexible methodology for stencil acceleration using register-mapped indirect streams. We demonstrate SARIS for various stencil codes on an eight-core RISC-V compute cluster with indirect stream registers, achieving significant speedups of 2.72x, near-ideal FPU utilizations of 81%, and energy efficiency improvements of 1.58x over an RV32G baseline on average. Scaling out to a 256-core manycore system, we estimate an average FPU utilization of 64%, an average speedup of 2.14x, and up to 15% higher fractions of peak compute than a leading GPU code generator.