2018/08/02 by Shaolin Xie, Michael Taylor, Xie, Shaolin +2 · 1 voice
Computer Science · #Bespoke #Chip #Computer architecture #Computer science #Core (optical fiber) #Embedded system #FOS: Computer and information sciences #Field-programmable gate array #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Multi-core processor #Parallel Computing and Optimization Techniques #Parallel computing #Telecommunications #VLSI and Analog Circuit Testing #cs.AR
paper · pdf · doi:10.48550/arxiv.1808.00650
Technical Report of Bespoke Silicon Group, University of Washington. http://bjump.org/manycore
openalex publication_date 2018/08/02 · arxiv published 2018/08/02 · arxiv created 2018/08/15 · arxiv updated 2018/08/16 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
The BaseJump Manycore Accelerator-Network is an open source mesh-based On-Chip-Network which is designed leveraging the Bespoke Silicon Group's 20+ years of experience in designing manycore architectures. It has been used in the 16nm 511-core RISC-V compatible Celerity chip Davidson et al. (2018), forming the basis of both a 1 GHz 496-core RISC-V manycore and a 10-core always-on low voltage complex. It was also used in the 180nm BSG Ten chip, which featured ten cores and a mesh that extends over off-chip links to an FPGA. To facilitate use by the open source community of the BaseJump Manycore network, we explain the ideas, protocols, interfaces and potential uses of the mesh network. We also show an example with source code that demonstrates how to integrate user designs into the mesh network.