2020/08/20 by Kris Nikov, Nikov, Kris, Mohammad Hosseinabady +10
Computer Science · #Distributed #Distributed and Parallel Computing Systems #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Parallel #Parallel Computing and Optimization Techniques #Performance (cs.PF) #and Cluster Computing (cs.DC)
paper · pdf · doi:10.48550/arxiv.2008.08883
openalex publication_date 2020/08/20 · openalex created_date 2022/07/26 · openalex updated_date 2026/08/01
This paper presents a methodology for simultaneous heterogeneous computing, named ENEAC, where a quad core ARM Cortex-A53 CPU works in tandem with a preprogrammed on-board FPGA accelerator. A heterogeneous scheduler distributes the tasks optimally among all the resources and all compute units run asynchronously, which allows for improved performance for irregular workloads. ENEAC achieves up to 17% performance improvement \ignoreand 14% energy usage reduction, when using all platform resources compared to just using the FPGA accelerators and up to 865% performance increase \ignoreand up to 89% energy usage decrease when using just the CPU. The workflow uses existing commercial tools and C/C++ as a single programming language for both accelerator design and CPU programming for improved productivity and ease of verification.