2022/01/20 by Su Zheng, Zheng, Su, Zhen Li +9
Engineering · Computer Science · #Ferroelectric and Negative Capacitance Devices #Advanced Neural Network Applications #Low-power high-performance VLSI design
paper · pdf · doi:10.48550/arxiv.2201.08022
We propose an optimization method for the automatic design of approximate multipliers, which minimizes the average error according to the operand distributions. Our multiplier achieves up to 50.24% higher accuracy than the best reproduced approximate multiplier in DNNs, with 15.76% smaller area, 25.05% less power consumption, and 3.50% shorter delay. Compared with an exact multiplier, our multiplier reduces the area, power consumption, and delay by 44.94%, 47.63%, and 16.78%, respectively, with negligible accuracy losses. The tested DNN accelerator modules with our multiplier obtain up to 18.70% smaller area and 9.99% less power consumption than the original modules.