Stateful Logic In-Memory Using Gain-Cell eDRAM

2025/06/29 by Barak Hoffer, Hoffer, Barak, Shahar Kvatinsky +1
Engineering · #Advanced Memory and Neural Computing #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #Low-power high-performance VLSI design #Semiconductor materials and devices

paper · pdf · doi:10.48550/arxiv.2506.23185

openalex publication_date 2025/06/29 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Modern data-intensive applications demand memory solutions that deliver high-density, low-power, and integrated computational capabilities to reduce data movement overhead. This paper presents the use of Gain-Cell embedded DRAM (GC-eDRAM) - a compelling alternative to traditional SRAM and eDRAM - for stateful, in-memory logic. We propose a circuit design that exploits GC-eDRAM's dual-port architecture and nondestructive read operation to perform logic functions directly within the GC-eDRAM memory array. Our simulation results demonstrate a 5us retention time coupled with a 99.5% success rate for computing the logic gates. By incorporating processing-in-memory (PIM) functionality into GC-eDRAM, our approach enhances memory and compute densities, lowers power consumption, and improves overall performance for data-intensive applications.

Citations

• MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic
• HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy
• Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks

Related

• Accelerating Bulk Bit-Wise X(N)OR Operation in Processing-in-DRAM Platform
• Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms,\n Future Research Directions
• Processing Data Where It Makes Sense: Enabling In-Memory Computation
• Memory-Centric Computing: Recent Advances in Processing-in-DRAM
• MCAIMem: a Mixed SRAM and eDRAM Cell for Area and Energy-efficient on-chip AI Memory