VeRLPy: Python Library for Verification of Digital Designs with\n Reinforcement Learning

2021/08/09 by Aebel Joe Shibu, S Sadhana, Shibu, Aebel Joe +5
Computer Science · Engineering · #Electrostatic Discharge in Electronics #Evolutionary Algorithms and Applications #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Machine Learning (cs.LG) #Software Engineering (cs.SE) #VLSI and Analog Circuit Testing

paper · pdf · doi:10.48550/arxiv.2108.03978

openalex publication_date 2021/08/09 · openalex created_date 2022/07/25 · openalex updated_date 2026/07/28

Abstract

Digital hardware is verified by comparing its behavior against a reference\nmodel on a range of randomly generated input signals. The random generation of\nthe inputs hopes to achieve sufficient coverage of the different parts of the\ndesign. However, such coverage is often difficult to achieve, amounting to\nlarge verification efforts and delays. An alternative is to use Reinforcement\nLearning (RL) to generate the inputs by learning to prioritize those inputs\nwhich can more efficiently explore the design under test. In this work, we\npresent VeRLPy an open-source library to allow RL-driven verification with\nlimited additional engineering overhead. This contributes to two broad\nmovements within the EDA community of (a) moving to open-source toolchains and\n(b) reducing barriers for development with Python support. We also demonstrate\nthe use of VeRLPy for a few designs and establish its value over randomly\ngenerated input signals.\n

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