2025/05/11 by Vasileios Titopoulos, Titopoulos, Vasileios, George Alexakis +5 · 1 voice
Computer Science · Engineering · #Coding theory and cryptography #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #cs.AR #graph theory and CDMA systems
paper · pdf · doi:10.48550/arxiv.2505.07112
openalex publication_date 2025/05/11 · arxiv published 2025/05/11 · arxiv updated 2025/05/30 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
RISC-V CPUs leverage the RVV (RISC-V Vector) extension to accelerate data-parallel workloads. In addition to arithmetic operations, RVV includes powerful permutation instructions that enable flexible element rearrangement within vector registers --critical for optimizing performance in tasks such as matrix operations and cryptographic computations. However, the diverse control mechanisms of these instructions complicate their execution within a unified datapath while maintaining the fixed-latency requirement of cryptographic accelerators. To address this, we propose a unified microarchitecture capable of executing all RVV permutation instructions efficiently, regardless of their control information structure. This approach minimizes area and hardware costs while ensuring single-cycle execution for short vector machines (up to 256 bits) and enabling efficient pipelining for longer vectors. The proposed design is integrated into an open-source RISC-V vector processor and implemented at 7 nm using the OpenRoad physical synthesis flow. Experimental results validate the efficiency of our unified vector permutation unit, demonstrating that it only incurs 1.5% area overhead to the total vector processor. Furthermore, this area overhead decreases to near-0% as the minimum supported element width for vector permutations increases.