2019/08/18 by Ning Qiao, Giacomo Indiveri, Qiao, Ning +1 · 1 citation
Computer Science · Engineering · #Advanced Memory and Neural Computing #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #Ferroelectric and Negative Capacitance Devices #Neural Networks and Reservoir Computing
paper · pdf · doi:10.48550/arxiv.1908.07874
openalex publication_date 2019/08/18 · openalex created_date 2019/08/29 · openalex updated_date 2026/07/28
Developing mixed-signal analog-digital neuromorphic circuits in advanced scaled processes poses significant design challenges. We present compact and energy efficient sub-threshold analog synapse and neuron circuits, optimized for a 28 nm FD-SOI process, to implement massively parallel large-scale neuromorphic computing systems. We describe the techniques used for maximizing density with mixed-mode analog/digital synaptic weight configurations, and the methods adopted for minimizing the effect of channel leakage current, in order to implement efficient analog computation based on pA-nA small currents. We present circuit simulation results, based on a new chip that has been recently taped out, to demonstrate how the circuits can be useful for both low-frequency operation in systems that need to interact with the environment in real-time, and for high-frequency operation for fast data processing in different types of spiking neural network architectures.