2021/01/02 by Sairam Sri Vatsavai, Vatsavai, Sairam Sri, Ishan Thakkar +1
Computer Science · Engineering · #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Machine Learning (cs.LG) #Neural Networks and Reservoir Computing #Optical Network Technologies #Photonic and Optical Devices
paper · pdf · doi:10.48550/arxiv.2101.00557
openalex publication_date 2021/01/02 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
To perform temporal and sequential machine learning tasks, the use of\nconventional Recurrent Neural Networks (RNNs) has been dwindling due to the\ntraining complexities of RNNs. To this end, accelerators for delayed feedback\nreservoir computing (DFRC) have attracted attention in lieu of RNNs, due to\ntheir simple hardware implementations. A typical implementation of a DFRC\naccelerator consists of a delay loop and a single nonlinear neuron, together\nacting as multiple virtual nodes for computing. In prior work, photonic DFRC\naccelerators have shown an undisputed advantage of fast computation over their\nelectronic counterparts. In this paper, we propose a more energy-efficient\nchip-scale DFRC accelerator that employs a silicon photonic microring (MR)\nbased nonlinear neuron along with on-chip photonic waveguides-based delayed\nfeedback loop. Our evaluations show that, compared to a well-known photonic\nDFRC accelerator from prior work, our proposed MR-based DFRC accelerator\nachieves 35% and 98.7% lower normalized root mean square error (NRMSE),\nrespectively, for the prediction tasks of NARMA10 and Santa Fe time series. In\naddition, our MR-based DFRC accelerator achieves 58.8% lower symbol error rate\n(SER) for the Non-Linear Channel Equalization task. Moreover, our MR-based DFRC\naccelerator has 98% and 93% faster training time, respectively, compared to an\nelectronic and a photonic DFRC accelerators from prior work.\n