2020/07/17 by Alfio Di Mauro, Francesco Conti, Di Mauro, Alfio +7
Engineering · Computer Science · #Advanced Memory and Neural Computing #Ferroelectric and Negative Capacitance Devices #Advanced Neural Network Applications
paper · pdf · doi:10.48550/arxiv.2007.08952
Binary Neural Networks (BNNs) have been shown to be robust to random\nbit-level noise, making aggressive voltage scaling attractive as a power-saving\ntechnique for both logic and SRAMs. In this work, we introduce the first fully\nprogrammable IoT end-node system-on-chip (SoC) capable of executing\nsoftware-defined, hardware-accelerated BNNs at ultra-low voltage. Our SoC\nexploits a hybrid memory scheme where error-vulnerable SRAMs are complemented\nby reliable standard-cell memories to safely store critical data under\naggressive voltage scaling. On a prototype in 22nm FDX technology, we\ndemonstrate that both the logic and SRAM voltage can be dropped to 0.5Vwithout\nany accuracy penalty on a BNN trained for the CIFAR-10 dataset, improving\nenergy efficiency by 2.2X w.r.t. nominal conditions. Furthermore, we show that\nthe supply voltage can be dropped to 0.42V (50% of nominal) while keeping more\nthan99% of the nominal accuracy (with a bit error rate ~1/1000). In this\noperating point, our prototype performs 4Gop/s (15.4Inference/s on the CIFAR-10\ndataset) by computing up to 13binary ops per pJ, achieving 22.8 Inference/s/mW\nwhile keeping within a peak power envelope of 674uW - low enough to enable\nalways-on operation in ultra-low power smart cameras, long-lifetime\nenvironmental sensors, and insect-sized pico-drones.\n