2021/06/09 by Cheng Liu, Cheng Chu, Liu, Cheng +13
Computer Science · Engineering · #Advanced Memory and Neural Computing #Advanced Neural Network Applications #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Radiation Effects in Electronics
paper · pdf · doi:10.48550/arxiv.2106.04772
openalex publication_date 2021/06/09 · openalex created_date 2021/06/22 · openalex updated_date 2026/07/28
Hardware faults on the regular 2-D computing array of a typical deep learning accelerator (DLA) can lead to dramatic prediction accuracy loss. Prior redundancy design approaches typically have each homogeneous redundant processing element (PE) to mitigate faulty PEs for a limited region of the 2-D computing array rather than the entire computing array to avoid the excessive hardware overhead. However, they fail to recover the computing array when the number of faulty PEs in any region exceeds the number of redundant PEs in the same region. The mismatch problem deteriorates when the fault injection rate rises and the faults are unevenly distributed. To address the problem, we propose a hybrid computing architecture (HyCA) for fault-tolerant DLAs. It has a set of dot-production processing units (DPPUs) to recompute all the operations that are mapped to the faulty PEs despite the faulty PE locations. According to our experiments, HyCA shows significantly higher reliability, scalability, and performance with less chip area penalty when compared to the conventional redundancy approaches. Moreover, by taking advantage of the flexible recomputing, HyCA can also be utilized to scan the entire 2-D computing array and detect the faulty PEs effectively at runtime.