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FPGA Implementations of Layered MinSum LDPC Decoders Using RCQ Message Passing

2021/04/19 by Caleb Terrill, Linfang Wang, Terrill, Caleb +11
Computer Science · Engineering · #Advanced Wireless Communication Techniques #Cooperative Communication and Network Coding #Error Correcting Code Techniques #FOS: Computer and information sciences #FOS: Electrical engineering #Hardware Architecture (cs.AR) #Information Theory (cs.IT) #Signal Processing (eess.SP) #electronic engineering #information engineering

paper · pdf · doi:10.48550/arxiv.2104.09480

openalex publication_date 2021/04/19 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Non-uniform message quantization techniques such as reconstruction-computation-quantization (RCQ) improve error-correction performance and decrease hardware complexity of low-density parity-check (LDPC) decoders that use a flooding schedule. Layered MinSum RCQ (L-msRCQ) enables message quantization to be utilized for layered decoders and irregular LDPC codes. We investigate field-programmable gate array (FPGA) implementations of L-msRCQ decoders. Three design methods for message quantization are presented, which we name the Lookup, Broadcast, and Dribble methods. The decoding performance and hardware complexity of these schemes are compared to a layered offset MinSum (OMS) decoder. Simulation results on a (16384, 8192) protograph-based raptor-like (PBRL) LDPC code show that a 4-bit L-msRCQ decoder using the Broadcast method can achieve a 0.03 dB improvement in error-correction performance while using 12% fewer registers than the OMS decoder. A Broadcast-based 3-bit L-msRCQ decoder uses 15% fewer lookup tables, 18% fewer registers, and 13% fewer routed nets than the OMS decoder, but results in a 0.09 dB loss in performance.

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