2024/12/23 by Melkamu Abay Mersha, Tsion Abay, Mersha, Melkamu +5
Computer Science · #Advanced Computational Techniques and Applications #Computational Physics and Python Applications #Data Mining Algorithms and Applications #FOS: Computer and information sciences #Hardware Architecture (cs.AR)
paper · pdf · doi:10.48550/arxiv.2412.17203
openalex publication_date 2024/12/23 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Virtual-to-physical address translation is a critical performance bottleneck in paging-based virtual memory systems. The Translation Lookaside Buffer (TLB) accelerates address translation by caching frequently accessed mappings, but TLB misses lead to costly page walks. Hardware and software techniques address this challenge. Hardware approaches enhance TLB reach through system-level support, while software optimizations include TLB prefetching, replacement policies, superpages, and page size adjustments. Prefetching Page Table Entries (PTEs) for future accesses reduces bottlenecks but may incur overhead from incorrect predictions. Integrating an Agile TLB Prefetcher (ATP) with SBFP optimizes performance by leveraging page table locality and dynamically identifying essential free PTEs during page walks. Predictive replacement policies further improve TLB performance. Traditional LRU replacement is limited to near-instant references, while advanced policies like SRRIP, GHRP, SHiP, SDBP, and CHiRP enhance performance by targeting specific inefficiencies. CHiRP, tailored for L2 TLBs, surpasses other policies by leveraging control flow history to detect dead blocks, utilizing L2 TLB entries for learning instead of sampling. These integrated techniques collectively address key challenges in virtual memory management.