2014/09/16 by Jun Lin, Zhiyuan Yan, Lin, Jun +1
Biochemistry, Genetics and Molecular Biology · Computer Science · Engineering · #Advanced Wireless Communication Techniques #DNA and Biological Computing #Error Correcting Code Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Information Theory (cs.IT)
paper · pdf · doi:10.48550/arxiv.1409.4744
openalex publication_date 2014/09/16 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Long polar codes can achieve the symmetric capacity of arbitrary binary-input discrete memoryless channels under a low complexity successive cancelation (SC) decoding algorithm. However, for polar codes with short and moderate code length, the decoding performance of the SC algorithm is inferior. The cyclic redundancy check (CRC) aided successive cancelation list (SCL) decoding algorithm has better error performance than the SC algorithm for short or moderate polar codes. In this paper, we propose an efficient list decoder architecture for the CRC aided SCL algorithm, based on both algorithmic reformulations and architectural techniques. In particular, an area efficient message memory architecture is proposed to reduce the area of the proposed decoder architecture. An efficient path pruning unit suitable for large list size is also proposed. For a polar code of length 1024 and rate (1)/(2), when list size L=2 and 4, the proposed list decoder architecture is implemented under a TSMC 90nm CMOS technology. Compared with the list decoders in the literature, our decoder achieves 1.33 to 1.96 times hardware efficiency.