Maximal Entropy Reduction Algorithm for SAR ADC Clock Compression

2018/11/07 by Molev-Shteiman, Arkady, Qi, Xiao-Feng
#FOS: Computer and information sciences #FOS: Electrical engineering #Networking and Internet Architecture (cs.NI) #Signal Processing (eess.SP) #electronic engineering #information engineering

paper · doi:10.48550/arxiv.1811.11102

Abstract

Reduction of comparison cycles leads to power savings of a successive-approximation-register (SAR) analog-to-digital converters (ADC). We establish that the lowest average number of comparison cycles of a SAR ADC approaches the entropy of the ADC output, and proposed a simple adaptive algorithm that approaches this lower bound. Today's SAR ADC uses binary search, which consumes more power than necessary for non-uniform input distributions commonly found in practice. We refer to a SAR ADC employing such algorithm the maximal entropy reduction (MER) ADC.

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