Gate--Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms

2024/01/07 by Dmytro Mishagli, Mishagli, Dmytro, Eugene Koskin +3
Computer Science · Engineering · #FOS: Computer and information sciences #FOS: Electrical engineering #Hardware Architecture (cs.AR) #Low-power high-performance VLSI design #Systems and Control (eess.SY) #VLSI and Analog Circuit Testing #VLSI and FPGA Design Techniques #electronic engineering #information engineering

paper · pdf · doi:10.48550/arxiv.2401.03588

openalex publication_date 2024/01/07 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

In this paper, the Statistical Static Timing Analysis (SSTA) is considered within the block--based approach. The statistical model of the logic gate delay propagation is systematically studied and the exact analytical solution is obtained, which is strongly non-Gaussian. The procedure of handling such (non-Gaussian) distributions is described and the corresponding algorithm for the critical path delay is outlined. Finally, the proposed approach is tested and compared with Monte Carlo simulations.

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