2025/05/16 by Christian Grewing, Arun Ashok, Grewing, Christian +9
Computer Science · Engineering · #Advanced Memory and Neural Computing #Emerging Technologies (cs.ET) #Evolutionary Algorithms and Applications #FOS: Computer and information sciences #Ferroelectric and Negative Capacitance Devices
paper · pdf · doi:10.48550/arxiv.2505.11009
openalex publication_date 2025/05/16 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
A system architecture is suggested for a System on Chip that will combine several different memristor-based, bio-inspired computation arrays with inter- and intra-chip communication. It will serve as a benchmark system for future developments. The architecture takes the special requirements into account which are caused by the memristor co-integration on commercial CMOS structures in a post processing step of the chip. The interface considers the necessary data bandwidth to monitor the internal Network on Chip at speed and provides enough flexibility to give different measurement options.