2023/09/19 by Dan Wu, Wu, Dan, Peng Chen +7
Computer Science · #Cloud Computing and Resource Management #Computer architecture #Computer science #Data parallelism #Efficient energy use #Exploit #FOS: Computer and information sciences #Graph #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Parallel Computing and Optimization Techniques #Parallel computing #Parallelism (grammar) #Speedup #Theoretical computer science
paper · pdf · doi:10.48550/arxiv.2309.10623
published in arXiv (Cornell University) (Cornell University)
openalex publication_date 2023/09/19 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Coarse-Grained Reconfigurable Arrays (CGRA) are promising edge accelerators due to the outstanding balance in flexibility, performance, and energy efficiency. Classic CGRAs statically map compute operations onto the processing elements (PE) and route the data dependencies among the operations through the Network-on-Chip. However, CGRAs are designed for fine-grained static instruction-level parallelism and struggle to accelerate applications with dynamic and irregular data-level parallelism, such as graph processing. To address this limitation, we present Flip, a novel accelerator that enhances traditional CGRA architectures to boost the performance of graph applications. Flip retains the classic CGRA execution model while introducing a special data-centric mode for efficient graph processing. Specifically, it exploits the natural data parallelism of graph algorithms by mapping graph vertices onto processing elements (PEs) rather than the operations, and supporting dynamic routing of temporary data according to the runtime evolution of the graph frontier. Experimental results demonstrate that Flip achieves up to 36× speedup with merely 19% more area compared to classic CGRAs. Compared to state-of-the-art large-scale graph processors, Flip has similar energy efficiency and 2.2× better area efficiency at a much-reduced power/area budget.