2023/07/14 by Syed Mohsin Abbas, Abbas, Syed Mohsin, Marwan Jalaleddine +5
Computer Science · Engineering · #Advanced Wireless Communication Techniques #Coding theory and cryptography #Error Correcting Code Techniques #FOS: Computer and information sciences #FOS: Electrical engineering #Hardware Architecture (cs.AR) #Information Theory (cs.IT) #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2307.07133
openalex publication_date 2023/07/14 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
GRAND features both soft-input and hard-input variants that are well suited to efficient hardware implementations that can be characterized with achievable average and worst-case decoding latency. This paper introduces step-GRAND, a soft-input variant of GRAND that, in addition to achieving appealing average decoding latency, also reduces the worst-case decoding latency of the corresponding hardware implementation. The hardware implementation results demonstrate that the proposed step-GRAND can decode CA-polar code (128,105+11) with an average information throughput of 47.7 Gbps at the target FER of ≤10-7. Furthermore, the proposed step-GRAND hardware is 10× more area efficient than the previous soft-input ORBGRAND hardware implementation, and its worst-case latency is (1)/(6.8)× that of the previous ORBGRAND hardware.