Asynchronous logic circuits and sheaf obstructions

2010/08/16 by Michael Robinson, Robinson, Michael · 1 citation
Computer Science · Engineering · #FOS: Computer and information sciences #Formal Methods in Verification #Hardware Architecture (cs.AR) #Low-power high-performance VLSI design #VLSI and Analog Circuit Testing

paper · pdf · doi:10.48550/arxiv.1008.2729

openalex publication_date 2010/08/16 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

This article exhibits a particular encoding of logic circuits into a sheaf formalism. The central result of this article is that there exists strictly more information available to a circuit designer in this setting than exists in static truth tables, but less than exists in event-level simulation. This information is related to the timing behavior of the logic circuits, and thereby provides a ``bridge'' between static logic analysis and detailed simulation.

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• Asynchronous Nonlinear Sheaf Diffusion for Multi-Agent Coordination

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