Efficient FPGA-based multipliers for F_3⁹7 and F_3^6*97

2007/08/22 by Jamshid Shokrollahi, Shokrollahi, Jamshid, Elisa Gorla +3
Computer Science · #Cryptography and Security (cs.CR) #FOS: Computer and information sciences #cs.CR

paper · pdf · doi:10.48550/arxiv.0708.3022

6 pages, 3 figures, to appear in the proceedings of FPL07

arxiv created 2007/08/22 · arxiv updated 2009/12/01

Abstract

In this work we present a new structure for multiplication in finite fields. This structure is based on a digit-level LFSR (Linear Feedback Shift Register) multiplier in which the area of digit-multipliers are reduced using the Karatsuba method. We compare our results with the other works in the literature for F_3⁹7. We also propose new formulas for multiplication in F_3^6*97. These new formulas reduce the number of F_3⁹7-multiplications from 18 to 15. The fields F_3⁹⁷ and F_3^6*97 are relevant in the context of pairing-based cryptography.

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