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Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs

2025/05/09 by S. F. Bush, Matthew DeLorenzo, Bush, Sam +5 · 1 citation
Computer Science · Decision Sciences · Materials Science · #Artificial Intelligence (cs.AI) #FOS: Computer and information sciences #Machine Learning in Materials Science #Physical Unclonable Functions (PUFs) and Hardware Security #Scientific Computing and Data Management

paper · pdf · doi:10.48550/arxiv.2505.06096

openalex publication_date 2025/05/09 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Limitations in Large Language Model (LLM) capabilities for hardware design tasks, such as generating functional Verilog codes, have motivated various fine-tuning optimizations utilizing curated hardware datasets from open-source repositories. However, these datasets remain limited in size and contain minimal checks on licensing for reuse, resulting in potential copyright violations by fine-tuned LLMs. Therefore, we propose an evaluation benchmark to estimate the risk of Verilog-trained LLMs to generate copyright-protected codes. To minimize this risk, we present an open-source Verilog dataset, FreeSet, containing over 220k files, along with the automated dataset curation framework utilized to provide additional guarantees of fair-use Verilog data. We then execute an LLM fine-tuning framework consisting of continual pre-training, resulting in a fine-tuned Llama model for Verilog, FreeV. Our results indicate that FreeV demonstrates the smallest risk of copyright-infringement among prior works, with only a 3% violation rate. Furthermore, experimental results demonstrate improvements in Verilog generation functionality over its baseline model, improving VerilogEval pass@10 rates by over 10%.

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